This invention relates to methods for recrystallizing metal in features of a semiconductor chip as part of a global planarization stepduring the manufacture of the chip, which by the method of recrystallization, also enhances the electromigration resistance of the film as well as alleviates the resistivity increase of metal lines in the regime below 200 nm due to grain boundary scattering and other interfacial effects.
The development of ultra-large-scale integration (ULSI) requires higher integration density with smaller design rules. Aluminum alloys have been widely used as metallization materials, but for ultra-large scale integration (ULSI) (e.g., the use of integrated circuits with more than a million logic gates), they are susceptible to electromigration and stress migration. The device performance has also become limited by the RC delay associated with aluminum alloy interconnects. An example of a multilayer ULSI application is illustrated in FIG. 7. In FIG. 7, features such as vias 710 and 712 connect one or more interconnect layers 702.
As ULSI technology progresses, the feature size (e.g. size of interconnects, vias, contacts) decreases while chip size increases. The lengths of features also increase, leading to higher resistances. The distance between adjacent features lessens. The capacitance between the adjacent features, therefore, increases although the capacitance between the feature and the ground substrate decreases, resulting in an increase in the total feature capacitance in the submicron range. Since both line resistance, R, and the capacitance associated with the dielectric, C, contribute to the interconnect delay, the total interconnect delay increases rapidly as the feature size decreases in the submicron range. The RC delay is given by:   RC  ≈            ρ              t        M              ⁢                            L          2                ⁢                  ϵ          ILD                            t        ILD            
where xcfx81, L, and tM, are the resistivity, length and thickness of the interconnect, and ∈ILD and tILD are the permittivity and thickness of the interlevel dielectric (ILD).
To reduce the RC delay, two approaches are used. One lowers C by adapting low permittivity (low-K) materials as interlevel dielectrics (ILD). Such materials include SiOF, SiOC, polymers, etc. The other lowers R by using interconnect materials with lower resistivity. A1 and A1 alloys have been used as interconnect materials for more than 30 years. Only three elements exhibit lower resistivity than aluminum: gold, silver, and copper. Among them, gold has the highest resistivity. Although silver has the lowest resistivity, it has poor electromigration reliability. Copper offers good mechanical and electrical properties. The resistivity of copper is about 40% better than that of aluminum. The self-diffusivity of copper is also the smallest among the four elements, resulting in improved reliability. Therefore, copper or copper alloys are promising materials for ULSI applications, such as the application illustrated in FIG. 7. One advantage of using copper and/or low-K dielectric is that the required number of layers 702 (FIG. 7) in a ULSI application can be reduced.
There are a number of ways in which semiconductors are manufactured. Referring to FIG. 1a, in a typical approach, known as the Damascene process, interlevel dielectric 102 is deposited. Next, trenches 104 are patterned by a method such as reactive ion etching (RIE). Then, optionally, a diffusion barrier 106 (FIG. 1b) is deposited. Optional diffusion barrier 106 is usually needed for copper and copper alloy applications because copper and copper alloys typically have poor adhesion to typical dielectric materials. Further, typical dielectric materials are not effective barriers for copper. Thus, copper can diffuse into the dielectric materials causing a degradation in the device performance.
After the diffusion barrier 106 has been deposited, metal (e.g., copper or a copper alloy) is deposited using a metal deposition technique, such as electrochemical deposition, to form interconnects 108 (FIG. 1c), vias, contacts or other features (not shown). Finally, excess copper or copper alloy (overburden 110; FIG. 1c) and barrier layers in the filled region are planarized. When overburden 110 is planarized, it becomes more even, and is no longer referred to as an overburden. Rather, it is referred to as a planarized metal surface over dielectric layer 102. Global planarization of overburden 110 is achieved by methods such as chemical mechanical polishing (CMP). Thus, after CMP, the metal above dielectric layer 102 is removed, leaving only metal inside trenches and vias (e.g., interconnect 108) (FIG. 1d). See, for example, Murarka et al., 1993, MRS Bulletin 18, 46-51; and Contolini et al., 1997, Solid State Technology 40, 155-162.
Referring to FIG. 2, a typical ULSI application has multiple layers of interconnects 108. Successive layers of interconnects 108 are connected by vias 202 (FIG. 2i). When metal such as copper or copper alloy is used for both interconnects 108 and vias 202, the dual Damascene process is often used to form the ULSI application. See, for example, Kaanta et al., 1991, IEEE VMIC Conf., pp. 144-52. The self-aligned dual Damascene process is illustrated in FIG. 2. In the process, via 202 and interconnect 108 shapes are reactive ion etch patterned on interlayer dielectrics by two etching steps. Then, copper or copper alloy deposition and chemical mechanical polishing is performed only once.
Regardless of whether the single or dual Damascene process is used, the final CMP step is made more difficult because of the uneven nature of overburden 110. In typical ULSI applications, the density of features, such as interconnects 108 and vias 202, is not uniform. In areas of high feature density, overburden 110 is thinner than in areas where feature density is relatively sparse. As feature size is reduced, overburden 110 uneveness becomes an even larger obstacle to achieving global planarization and leads to the undesired properties of non-uniform and inconsistent metal lines resistivities during manufacturing.
Another obstacle in the use of copper or copper alloy in ULSI applications is their electromigration properties. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of atoms in the direction of electron flow. Electromigration leads to degradation in interconnect reliability.
Still another obstacle in the use of copper and copper alloys in ULSI applications is stress migration resistance. Stress migration resistance arises due to a high degree of intrinsic stress in copper or copper alloy interconnects, vias, contacts, as well as other features created using electrochemical deposition (ECD). ECD copper grains are very small. For deposition purposes, this grain size is advantageous because it facilitates deposition into deep features in the ULSI application that have very high aspect ratios without the formation of gaps or other voids. However, the resulting fine-grained film deposition is under a high degree of intrinsic stress due to an excess of vacancies, dislocations, and other crystalline imperfections. See, for example, Ritzdorf et al, 1998, IEEE Proc. Int""l Interconnect Tech. Conf., pp. 106-108.
In some ULSI applications, there are more than 100 line segments connecting devices, each line carrying current densities as high as 0.4 mA/cm2. See Thompson and Lloyd, (June 1993), MRS Bulletin pp. 19-24. Compared to the maximum current density for household wiring of about 102 A/cm2, theses are significantly higher current densities. At such large current densities, electrons scatter with metal atoms, and the transferred momentum results in atomic migration. As atoms electromigrate, voids are formed at upstream and hillocks are formed at downstream of electron flow (FIG. 3). Voids and hillocks will grow and eventually cause open circuit or short circuit failure. It is known that larger grain size reduces problems with electromigration. However, techniques such as electroplating produce very small grain size.
In summary, the condition of copper and/or copper alloy (e.g., a copper aluminum alloy) that has been electrochemically deposited in ULSI applications is undesirable because of difficulties with subsequent CMP polishing of uneven overburden layers as well as the electromigration and stress migration resistance properties of copper and/or copper alloy. To remedy these deficiencies, Graham et al., 2000, Semiconductor Fabtech 11th Edition, pp. 279-282, http://www.fabtech.org, proposed a rapid thermal anneal driven recrystallization scheme in which electroplated copper is recrystallized. Graham et al. report that rapid thermal annealing of electroplated copper results in recrystallization of the copper. Furthermore, the recrystallized copper has larger grain sizes.
Although the Graham et al. approach appears promising, there are drawbacks. First, the approach requires exposing the entire structure to elevated temperatures, which could damage the structure. Second, the Graham et al. data indicates that higher temperatures are required to recrystallize copper in 0.25 micron features as opposed to 0.75 micron features. Thus, the Graham et al. approach requires increasing temperatures as feature sizes are made smaller. Thus, the Graham et al. approach may not work for feature sizes that are used in current and planned ULSI applications.
According to the above background, what is needed in the art are improved methods for recrystallizing metals used in interconnects, vias, contacts, as well as other features of ULSI applications in order to facilitate planarization of interconnect layers and improve the electromigration, stress migration resistance, and resistivity increase of these metals. Such techniques are particularly needed in applications in which metals are embedded in subhundred nanometer trenches which incur substantial resistivity increases due to grain boundary scattering effects.
The present invention provides an improved method for recrystallizing metals used in interconnects, vias, contacts, as well as other features of ULSI applications. In the present invention, a laser is used to recrystallize metal in order to facilitate planarization of interconnect layers, to improve the electromigration and stress migration resistance properties of these metals, and to alleviate the resistivity increase in metals embedded in small trenches (e.g., 200 nm or less, 100 nm or less) due to grain boundary scattering effects.
One aspect of the present invention provides a method for manufacturing a semiconductor structure having an interlevel dielectric. The method comprises (i) patterning features in the interlevel dielectric, (ii) depositing a metal into the features, and (iii) recrystallizing metal in the features using a laser. In some embodiments, the features are patterned by reactive ion etching (RIE). In some embodiments, the features comprise any combination of interconnects, vias, and contacts. In some embodiments, the deposition is performed by physical vapor deposition (e.g, RF sputtering, bias sputtering, thermal assisted bias sputtering), evaporation, ion beam deposition, thermally assisted ion cluster deposition, chemical vapor deposition, electroless plating, electroplating, electrochemical deposition, etc).
In some embodiments, the method further comprises coating the features with a diffusion barrier prior to the depositing step. In some embodiments, the method further comprises removing an overburden of the metal by chemical mechanical polishing (CMP).
In some embodiments, the recrystallizing step comprises exposing the metal in the features to a laser annealing protocol that includes exposing the metal to a laser having a predetermined wavelength. In some embodiments, the wavelength is selected from the range of 150 nm to 900 nm. In some embodiments, the wavelength is selected from the range of 150 nm to 450 nm. In some embodiments, the laser annealing protocol comprises a single laser pulse that is selected from a pulse length range, wherein a lower boundary of the pulse length range is determined by a requirement that the metal in the feature melt for a period of time. In some embodiments, the laser used in the laser annealing protocol has an output pulse energy of about 1.0 joules/cm2 to about 4.0 joules/cm2.
Another aspect of the present invention provides a semiconductor structure having an interlevel dielectric. The semiconductor structure is made by a process comprising (i) patterning features in the interlevel dielectric, (ii) depositing a metal into the features, (iii) melting and recrystallizing metal in the features using a laser. In some embodiments, the process further comprises coating the features with a diffusion barrier prior to the depositing step.
In still other embodiments, the process further comprises removing an overburden of the metal by chemical mechanical polishing (CMP).